1. Field of the Invention
The present invention relates to a technology for supporting layout design of a semiconductor integrated circuit.
2. Description of the Related Art
Secular change called stress migration breaks vias in a semiconductor integrated circuit to shorten the life of the integrated circuit. Such phenomenon has been long been recognized. Stress migration is a phenomenon that bubbles called vacancies caused in a metal wiring migrate due to the gradient of stress generated in the wiring. These vacancies migrate to be concentrated on a via to grow a gap called void. The growth of the gap ultimately breaks the via.
A semiconductor device in which the occurrence of wire breaking failures at conductive vias due to stress migration is reduced and a manufacturing method thereof have been achieved as a technique for alleviating stress migration (for example, Japanese Patent Application Laid-Open Publication No. 2005-142423).
The conventional techniques, however, are aimed at the alleviation of the stress migration occurring only on a wide wiring. This is because stress migration had been believed to occur on only the via that is connected to a wide wire. An effective means for alleviating stress migration, therefore, has not been provided for a narrow wiring, which leaves a problem unsolved that a via breaks to shorten the life of a semiconductor integrated circuit.
A method of enhancing resistance against stress migration by duplicating vias (redundant vias) has been widely known. This method, however, has a disadvantage in that space is limited for inserting duplicate vias, thereby allowing only 60% to 90% of single vias to be formed in the redundant vias. This method is applicable to less number of vias, compared to a dummy via insertion method that does not limit insertion points and that can be applied easily to more than 99% of vias.